Setting log file to 'C:/Lattice/Kurs26/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/decoder_7seg.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/display_multiplex.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/edge_detector.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/slave_spi.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/strobe_generator.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/synchronizer.v' (VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs26/impl1/source/top.v' INFO - C:/Lattice/Kurs26/impl1/source/top.v(5,8-5,11) (VERI-1018) compiling module 'top' INFO - C:/Lattice/Kurs26/impl1/source/top.v(5,1-73,10) (VERI-9000) elaborating module 'top' INFO - C:/Lattice/Kurs26/impl1/source/slave_spi.v(5,1-105,10) (VERI-9000) elaborating module 'SlaveSPI_uniq_1' INFO - C:/Lattice/Kurs26/impl1/source/display_multiplex.v(4,1-77,10) (VERI-9000) elaborating module 'DisplayMultiplex_uniq_1' INFO - C:/Lattice/Kurs26/impl1/source/synchronizer.v(4,1-28,10) (VERI-9000) elaborating module 'Synchronizer_uniq_1' INFO - C:/Lattice/Kurs26/impl1/source/edge_detector.v(4,1-24,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_1' INFO - C:/Lattice/Kurs26/impl1/source/edge_detector.v(4,1-24,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_2' INFO - C:/Lattice/Kurs26/impl1/source/strobe_generator.v(4,1-41,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_1' INFO - C:/Lattice/Kurs26/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_1' Done: design load finished with (0) errors, and (0) warnings