Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Mon Jun 24 13:59:53 2024

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
            590 items scored, 106 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 1.413ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \SlaveSPI_inst/Synchronizer_inst/R2_i2  (from Clock_c +)
   Destination:    FD1P3AX    D              \SlaveSPI_inst/DataToSend_i7  (to Clock_c +)

   Delay:                   6.267ns  (27.9% logic, 72.1% route), 4 logic levels.

 Constraint Details:

      6.267ns data_path \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i7 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 1.413ns

 Path Details: \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i7

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \SlaveSPI_inst/Synchronizer_inst/R2_i2 (from Clock_c)
Route         7   e 1.303                                  SyncCS
LUT4        ---     0.448              B to Z              \SlaveSPI_inst/EdgeDetectorCS/i1_2_lut_rep_13
Route         5   e 1.174                                  \SlaveSPI_inst/n881
LUT4        ---     0.448              A to Z              \SlaveSPI_inst/TransmissionStart_o_I_0_4_lut_rep_9
Route         7   e 1.255                                  \SlaveSPI_inst/n814
LUT4        ---     0.448              C to Z              \SlaveSPI_inst/DataToSend_7__I_0_37_i8_3_lut
Route         1   e 0.788                                  \SlaveSPI_inst/DataToSend_7__N_48[7]
                  --------
                    6.267  (27.9% logic, 72.1% route), 4 logic levels.


Error:  The following path violates requirements by 1.413ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \SlaveSPI_inst/Synchronizer_inst/R2_i2  (from Clock_c +)
   Destination:    FD1P3AX    D              \SlaveSPI_inst/DataToSend_i6  (to Clock_c +)

   Delay:                   6.267ns  (27.9% logic, 72.1% route), 4 logic levels.

 Constraint Details:

      6.267ns data_path \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i6 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 1.413ns

 Path Details: \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i6

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \SlaveSPI_inst/Synchronizer_inst/R2_i2 (from Clock_c)
Route         7   e 1.303                                  SyncCS
LUT4        ---     0.448              B to Z              \SlaveSPI_inst/EdgeDetectorCS/i1_2_lut_rep_13
Route         5   e 1.174                                  \SlaveSPI_inst/n881
LUT4        ---     0.448              A to Z              \SlaveSPI_inst/TransmissionStart_o_I_0_4_lut_rep_9
Route         7   e 1.255                                  \SlaveSPI_inst/n814
LUT4        ---     0.448              C to Z              \SlaveSPI_inst/DataToSend_7__I_0_37_i7_3_lut
Route         1   e 0.788                                  \SlaveSPI_inst/DataToSend_7__N_48[6]
                  --------
                    6.267  (27.9% logic, 72.1% route), 4 logic levels.


Error:  The following path violates requirements by 1.413ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \SlaveSPI_inst/Synchronizer_inst/R2_i2  (from Clock_c +)
   Destination:    FD1P3AX    D              \SlaveSPI_inst/DataToSend_i5  (to Clock_c +)

   Delay:                   6.267ns  (27.9% logic, 72.1% route), 4 logic levels.

 Constraint Details:

      6.267ns data_path \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i5 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 1.413ns

 Path Details: \SlaveSPI_inst/Synchronizer_inst/R2_i2 to \SlaveSPI_inst/DataToSend_i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \SlaveSPI_inst/Synchronizer_inst/R2_i2 (from Clock_c)
Route         7   e 1.303                                  SyncCS
LUT4        ---     0.448              B to Z              \SlaveSPI_inst/EdgeDetectorCS/i1_2_lut_rep_13
Route         5   e 1.174                                  \SlaveSPI_inst/n881
LUT4        ---     0.448              A to Z              \SlaveSPI_inst/TransmissionStart_o_I_0_4_lut_rep_9
Route         7   e 1.255                                  \SlaveSPI_inst/n814
LUT4        ---     0.448              C to Z              \SlaveSPI_inst/DataToSend_7__I_0_37_i6_3_lut
Route         1   e 0.788                                  \SlaveSPI_inst/DataToSend_7__N_48[5]
                  --------
                    6.267  (27.9% logic, 72.1% route), 4 logic levels.

Warning: 6.413 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock_c]                 |     5.000 ns|     6.413 ns|     4 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
Strobe_o_N_142                          |      16|      64|     60.38%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
n24                                     |       1|      64|     60.38%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
n741                                    |       1|      64|     60.38%
                                        |        |        |
\SlaveSPI_inst/n814                     |       7|      42|     39.62%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
Counter[0]                              |       2|      16|     15.09%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
Counter[3]                              |       2|      16|     15.09%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
Counter[4]                              |       2|      16|     15.09%
                                        |        |        |
\DisplayMultiplex_inst/StrobeGenerator0/|        |        |
Counter[13]                             |       2|      16|     15.09%
                                        |        |        |
\SlaveSPI_inst/n698                     |       2|      14|     13.21%
                                        |        |        |
\SlaveSPI_inst/n881                     |       5|      14|     13.21%
                                        |        |        |
\SlaveSPI_inst/n882                     |       2|      14|     13.21%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 106  Score: 112966

Constraints cover  617 paths, 121 nets, and 336 connections (59.7% coverage)


Peak memory: 57913344 bytes, TRCE: 1708032 bytes, DLYMAN: 167936 bytes
CPU_TIME_REPORT: 0 secs