Place & Route TRACE Report

Loading design for application trce from file kurs26_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Thu Jun 27 13:12:45 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs26_impl1.twr -gui -msgset C:/Lattice/Kurs26/promote.xml Kurs26_impl1.ncd Kurs26_impl1.prf 
Design file:     kurs26_impl1.ncd
Preference file: kurs26_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 454 items scored, 0 timing errors detected. Report: 168.606MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 454 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 34.069ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i6 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 Delay: 5.683ns (31.1% logic, 68.9% route), 4 logic levels. Constraint Details: 5.683ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.069ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.683 (31.1% logic, 68.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.069ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (to Clock_c +) Delay: 5.683ns (31.1% logic, 68.9% route), 4 logic levels. Constraint Details: 5.683ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.069ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.683 (31.1% logic, 68.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.069ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i2 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i1 Delay: 5.683ns (31.1% logic, 68.9% route), 4 logic levels. Constraint Details: 5.683ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.069ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.683 (31.1% logic, 68.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.069ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i4 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 Delay: 5.683ns (31.1% logic, 68.9% route), 4 logic levels. Constraint Details: 5.683ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.069ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.683 (31.1% logic, 68.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 Delay: 5.471ns (32.3% logic, 67.7% route), 4 logic levels. Constraint Details: 5.471ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.281ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.058 R8C14C.F0 to R7C14B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.471 (32.3% logic, 67.7% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i14 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 Delay: 5.471ns (32.3% logic, 67.7% route), 4 logic levels. Constraint Details: 5.471ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.281ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.058 R8C14C.F0 to R7C14D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.471 (32.3% logic, 67.7% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i12 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i11 Delay: 5.471ns (32.3% logic, 67.7% route), 4 logic levels. Constraint Details: 5.471ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.281ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.058 R8C14C.F0 to R7C14C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.471 (32.3% logic, 67.7% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.281ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 Delay: 5.471ns (32.3% logic, 67.7% route), 4 logic levels. Constraint Details: 5.471ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.281ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 1.187 R7C14D.Q0 to R8C13A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.452 R8C13A.B0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.058 R8C14C.F0 to R7C14A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.471 (32.3% logic, 67.7% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C14A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.376ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i4 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 Delay: 5.376ns (32.8% logic, 67.2% route), 4 logic levels. Constraint Details: 5.376ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.376ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13C.CLK to R7C13C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 (from Clock_c) ROUTE 2 0.880 R7C13C.Q0 to R8C13A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R8C13A.A0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.376 (32.8% logic, 67.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.376ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i2 (to Clock_c +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i1 Delay: 5.376ns (32.8% logic, 67.2% route), 4 logic levels. Constraint Details: 5.376ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.376ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13C.CLK to R7C13C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_0 (from Clock_c) ROUTE 2 0.880 R7C13C.Q0 to R8C13A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R8C13A.A0 to R8C13A.F0 SLICE_61 ROUTE 1 0.579 R8C13A.F0 to R8C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/n24 CTOF_DEL --- 0.452 R8C13A.A1 to R8C13A.F1 SLICE_61 ROUTE 1 0.882 R8C13A.F1 to R8C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n741 CTOF_DEL --- 0.452 R8C14C.B0 to R8C14C.F0 SLICE_29 ROUTE 9 1.270 R8C14C.F0 to R7C13B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142 (to Clock_c) -------- 5.376 (32.8% logic, 67.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 42 2.001 20.PADDI to R7C13B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Report: 168.606MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 25.000 MHz| 168.606 MHz| 4 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 42 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 454 paths, 1 nets, and 267 connections (55.39% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2 Thu Jun 27 13:12:45 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs26_impl1.twr -gui -msgset C:/Lattice/Kurs26/promote.xml Kurs26_impl1.ncd Kurs26_impl1.prf Design file: kurs26_impl1.ncd Preference file: kurs26_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 454 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 454 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i7 (from Clock_c +) Destination: FF Data in Byte0_i0_i7 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SlaveSPI_inst/SLICE_93 to SLICE_66 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SlaveSPI_inst/SLICE_93 to SLICE_66: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C11C.CLK to R10C11C.Q0 SlaveSPI_inst/SLICE_93 (from Clock_c) ROUTE 1 0.152 R10C11C.Q0 to R10C11B.M1 DataReceived_7 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_93: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_66: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/Synchronizer_inst/R2_i0 (from Clock_c +) Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i0 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SlaveSPI_inst/Synchronizer_inst/SLICE_42 to SlaveSPI_inst/SLICE_72 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SlaveSPI_inst/Synchronizer_inst/SLICE_42 to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C12A.CLK to R8C12A.Q1 SlaveSPI_inst/Synchronizer_inst/SLICE_42 (from Clock_c) ROUTE 1 0.152 R8C12A.Q1 to R8C12B.M0 SlaveSPI_inst/SyncMOSI (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/Synchronizer_inst/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i6 (from Clock_c +) Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i7 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SlaveSPI_inst/SLICE_93 to SlaveSPI_inst/SLICE_93 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SlaveSPI_inst/SLICE_93 to SlaveSPI_inst/SLICE_93: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C11C.CLK to R10C11C.Q1 SlaveSPI_inst/SLICE_93 (from Clock_c) ROUTE 2 0.154 R10C11C.Q1 to R10C11C.M0 DataReceived_6 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_93: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SlaveSPI_inst/SLICE_93: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i0 (from Clock_c +) Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i1 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SlaveSPI_inst/SLICE_72 to SlaveSPI_inst/SLICE_72 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SlaveSPI_inst/SLICE_72 to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q0 SlaveSPI_inst/SLICE_72 (from Clock_c) ROUTE 2 0.154 R8C12B.Q0 to R8C12B.M1 DataReceived_0 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i1 (from Clock_c +) Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i2 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SlaveSPI_inst/SLICE_72 to SlaveSPI_inst/SLICE_68 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SlaveSPI_inst/SLICE_72 to SlaveSPI_inst/SLICE_68: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q1 SlaveSPI_inst/SLICE_72 (from Clock_c) ROUTE 2 0.154 R8C12B.Q1 to R8C12C.M0 DataReceived_1 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SlaveSPI_inst/SLICE_68: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C12C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i6 (from Clock_c +) Destination: FF Data in Byte0_i0_i6 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SlaveSPI_inst/SLICE_93 to SLICE_66 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SlaveSPI_inst/SLICE_93 to SLICE_66: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C11C.CLK to R10C11C.Q1 SlaveSPI_inst/SLICE_93 (from Clock_c) ROUTE 2 0.154 R10C11C.Q1 to R10C11B.M0 DataReceived_6 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_93: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_66: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/Synchronizer_inst/R2_i2 (from Clock_c +) Destination: FF Data in SlaveSPI_inst/EdgeDetectorCS/Previous_13 (to Clock_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay SLICE_45 to SLICE_45 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path SLICE_45 to SLICE_45: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C13C.CLK to R8C13C.Q0 SLICE_45 (from Clock_c) ROUTE 7 0.155 R8C13C.Q0 to R8C13C.M1 SyncCS (to Clock_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C13C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C13C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i4 (from Clock_c +) Destination: FF Data in Byte0_i0_i4 (to Clock_c +) Delay: 0.289ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.289ns physical path delay SlaveSPI_inst/SLICE_67 to SLICE_65 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.308ns Physical Path Details: Data path SlaveSPI_inst/SLICE_67 to SLICE_65: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C11D.CLK to R8C11D.Q0 SlaveSPI_inst/SLICE_67 (from Clock_c) ROUTE 2 0.156 R8C11D.Q0 to R10C11D.M0 DataReceived_4 (to Clock_c) -------- 0.289 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SlaveSPI_inst/SLICE_67: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R8C11D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_65: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R10C11D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C14D.CLK to R7C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 (from Clock_c) ROUTE 2 0.132 R7C14D.Q0 to R7C14D.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_13 CTOF_DEL --- 0.101 R7C14D.A0 to R7C14D.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_1 ROUTE 1 0.000 R7C14D.F0 to R7C14D.DI0 DisplayMultiplex_inst/StrobeGenerator0/n7 (to Clock_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R7C14D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R7C14D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 (from Clock_c +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 (to Clock_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C14A.CLK to R7C14A.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 (from Clock_c) ROUTE 2 0.132 R7C14A.Q0 to R7C14A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.101 R7C14A.A0 to R7C14A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 ROUTE 1 0.000 R7C14A.F0 to R7C14A.DI0 DisplayMultiplex_inst/StrobeGenerator0/n13 (to Clock_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R7C14A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 42 0.773 20.PADDI to R7C14A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 0.000 ns| 0.304 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 42 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 454 paths, 1 nets, and 267 connections (55.39% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------